Hello Friend! I changed my project. I created a component with 24 differential inputs and 48 output data buses. Data from channels I and Id are fed to the input. Differential clock CLK_I is connected to the input for data I and Id. Differential clock CLK_Q is connected to the input for data Q and Qd. I turned off the channel Q. Data is transmitted only on the I and I channel. Replacing the IP core of the SelectIO did not change the result. The data channel is inverse between measurements. I turned on the ADC test mode to check the channels. The test is normal. What is the problem? If the FPGA does not work correctly, why does the test pass normally? I looked at the data from the ADC. I sent the channel I data to ILA. To view the data that is negedge clk_I, I recorded the data in a 12-bit register clocked negedge clk_I. I sent the recorded data to ILA. The result is the same. Even and odd data are inverse.
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