Hello： Thank you very much for your answer, I will explain the details: Case 1: The clock is 156.25mhz, 8 LANEs, 8 times interpolation, the output rate of the DAC is 1250mhz, and the registers 100 to 108 have no warning and can work normally. Case 2: The clock becomes 160mhz, 8 lanes, 8 times interpolation, the DAC output rate is 1280mhz, and the readback value of registers 100 to 107 is "0703". Indicates "code synchronization error". The FPGA sent the |K| code and the K code received by the DAC is incorrect. Note: The PLL is not used in either case and no registers are changed for the DAC. LMFS (8411). How can I adjust the registers of the DAC?
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