Part Number: DAC5675AEVM Hello, I am testing DAC5675A EVM. The problem is that no DAC output signal occurs. The state of J8 was always 'HIGH' and never changed. I setup test environment following ' DAC5675A EVM Quick Start Guide' document. At 1st trial, I send 20MHz single tone at 400MSPS. No DAC output signal was shown on J8. At 2nd trial, I send 2MHz signle tone at 50MSPS. No DAC output signal was shown on J8. I checked CMOS data signal from TSW1400. Those signals looked fine - high and low level were normal CMOS level. Then I checked output of U3( SN65LVDS387 ). Those signals looked normal LVDS signal levels. And I checked CLK and CLKC pins on DAC5675A . Those signals looked fine. CLKC was negative to CLK. I made a new pattern file not to change data bit states. New pattern file contains one column / 4096 rows and all values were 0. After send a new pattern file, I was not able to notice any change on J8. I checked some signals as below -. CMOS data D[13:1] were all '0' and D0 was '1' -. EXTIO pin was about 1.2V -. BIASJ pin was about 1.2V. -. SLEEP pin was '0' -. IOUT1 and IOUT2 pin: Both of them were above 3V. I don't know why IOUT1 and IOUT2 are same level even D[13:0] is 1 Please give me any advice relating this issue.
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