Hi Jim! Sorry for not immediately answering, I was busy. I put aside this board with ADC12D1600 ADC. I have a board with ADC ADC08D1500 and FPGA. I decided to check correctly I accept the data from the ADC. This ADC is similar to the ADC12D1600 , it is only 8 bit, the speed is lower and the control is slightly different. I checked my design. I received the correct data in DDR mode. Now I’m sure that I’m doing everything right. I checked the connection of the ADC and PCB. My ADC12D1600 Sampling Clock CLK = 800MHz data clk DCLK = 200 MHz. I connected DCLK to the pin FPGA DCLK = 200MHz and measured the frequency on the pin. I will try to lower the Sampling Clock. At 50 Mhz, should I set bit 8 in the Configuration Register?
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