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Forum Post: RE: TINA/Spice/ADC12DL3200: SYSREF processing activity

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Hi Daniele You say that you are seeing a constant phase delta between the different ADCs on the board, but that the delta phase is not good for your system. Are the CLK signals delivered to the 4 ADCs routed with matched delays so they are all phase aligned? How much phase delta are you seeing (comparing the same DxCLK or DxSTR signals on each of the 4 ADCs)? Even if the input CLK signals are phase aligned there will be some differences due to part to part variation in Tod (output delay) between the 4 ADCs. Best regards, Jim B

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