Hi Jim, The clocks are distributed using several buffers and switchs and this network has a delay that is not easy to manage. This is one of the reasons to manage the delay of the SYSREF signals. The CLK and input signals are routed with matched traces and simulated using CST Microwave SW. Moreover the ADCs uses different inputs: 2 ADC use INA inputs and and 2 ADC use INB inputs. In particular, if the board distributes the same input signal, clock and SYSREF at two different ADCs (LDEMUX = 1 and LFRAME = 8) and one ADC uses INA input and the other ADC uses INB input, Is there a specific difference between the phase of input signals acquired? Today I will do others measurement to study the results and maybe I understand the problems. Regards, Daniele
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