Hi customer have another question as below: we have another further question need your help on the DAC7311DCKR clock signal. I find in the datasheet that, the CPOL bit is 0, while CPHA bit is 1, and as I know in SPI definition, this may mean the Clock signal should be low level when idle ? please help confirm this. Basing on our issue in customer side, in which the OVP is triggered when adjusting the output voltage from 18V to 19V, while the OVP point is 38V. I have one concern, does the wrong clock signal logical level when idle will cause this OVP if the minimum SCLK high&low time is not met. I conducted test with the SCLK logical level when idle following the CPOL is 0, CPHA is 1, and found if the SCLK high&low time not met, the SPI may fail to adjust voltage. in customer side, the SCLK logical level when idle is high , which may not follow the spec, and OVP triggered when SCLK signal high&low time not met. so, would you please help confirm if the wrong logical level when idle will cause the DAC output max voltage? which will cause voltage be adjusted to the maximum voltage and trigger OVP.
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