Hi Mark, 1/ As you can see in figure 12, the two integrators of each input work one after the other, in ping-pong. These are 2 consecutive samples of the same channel. Hence the output samples come one after the other as can be seen in figure 11. These are 2 different samples each coming after the corresponding DVALID. The zoom in of what happens after DVALID is figure 17. 2/ The sampling (actually more the integration) is done by the integrators, either all 32 of the A side or all 32 of the B side (depends on what cycle of the CONV you are, high or low). As explained in the DS: "the output of the integrators from one side of the inputs will be digitized while the other 32 integrators are in the integration mode". It is simultaneous (all the A at one shot, all the B at the next shot, and back). The 32 that integrated in the previous cycle, hold the sampled data internally (while the other set of integrators is integrating) and then the ADCs convert their outputs, these get stored in a shift register, DVALID is signaled and then its data can be read out. Whether there is one or more ADCs working internally to do that is actually irrelevant (it is more an FYI). In this case we choose to have one ADC for every two channels. The important thing is that they crank the work in one sample time (half of the CONV period). Obviously the ADC is actually working at 2x faster than the integration time (as the same ADC got to cover 2 channels). 3/ A and B are consecutive samples of the same channel. Two different samples. One after the other every 160us. I think the confusion may be coming from thinking that the CONV period is the sampling rate. The sampling rate is by definition the rate at what the samples are taken. Every sample is taken from one edge of CONV to the next edge, hence, at 2x the CONV frequency. Hope that clears things up... Eduardo
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