Forum Post: AFE5801- DCLK 60 MHz or 120 MHz?

Please refer to pg. 9 of AFE5801 datasheet. I am debugging subroutines to: deserialize the LVDS data on DCLK (bit clock) rising & falling edge { inner While Loop } capture the complete word on FCLK (frame clock) rising edge { outer While Loop } Assume FCLK (frame clock) = 10 MHz. Per the figure, DCLK= 6 * 10 or 60 MHz. I am confused on the rate at which the inner or deserialize While Loop should execute. DCLK is DDR, i.e. we strobe the data on DCLK rising and falling edge. Should the inner or deserialize While Loop run at 120 MHz {60 *2 (rising + falling), DDR} or 60 MHz in this case? Thanks, Mohit Kapur