Hello Chuck: Thanks for the clarification. Assuming FCLK (frame clock) = 10 MHz, rate at which the inner or deserialize While Loop should execute is 60 MHz. FYI- We need to build DDR logic block + Serial-Parallel Shift Register ourselves in LabVIEW, not part of NI logic library. The App Note is very helpful, thank you! I will start another thread for separate topic since I do not find the answer in the forums. Thanks, Mohit Kapur
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