Hi Chuck, Thanks for replying so quickly. Yes, I can confirm that we are applying the SEN/SPI_DIG_EN sequence shown in the datasheet (although we are using the Rev "E" datasheet so this sequence is given in section 8.5.1.3.5 on p50 and in section 8.6.2.1.1 on p71). There are no relative timings given for the SEN and SPI_DIG_EN though and so we have tried various delays between SPI_DIG_EN going low and SEN going low, and also when the signals go high again. As I said before, we can read the demod register contents most of the time (in most of our test code's loops) but sometimes (in some loops) the data bits returned are zero. This says to me that there is no fundamental error in our access method, Another test I performed since my first post was to re-read the register contents back three times for every write. I can see some return values varying from zero to a reasonable value within the 3 reads. I also see some return values returning the *previous* value I wrote to that register, from which I conclude that both the write and the read are unreliable. Your further thoughts will be appreciated. Duncan
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