Forum Post: RE: AFE5805 interface for ASIC or FPGA

Hi Xiaochen, I am using the Spartan 6 FPGA and am interfacing to the AFE5808A . For the most part my deserializer is working, but I get an occasional missing bit while using the ramp pattern on the 5808A. I understand that Xilinx has a complete solution for interfacing to LVDS ADCs (i.e. AFEs). Can you provide the link to this. The first link above is broken. Thanks, Greg