Hi Martin, I've got the following response from a more experienced colleague with regard to your LM98725 questions. I've shown the responses in color below. When I provide 5MHz INCLK to LM98725 the output clock from PHIA1 whould also be 5MHz for the sensor or do I need to configure/program it? For 5 MHz input clock and configuration set to INCLK at PIXCLK rate, the PHIA1 frequency can be programmed to be at 2.5, 5 MHz, or higher frequencies. Settings controlling the waveform frequency for PHIA are in Register Page 6, Address 0-5 and Address 1Eh. These must be set as needed, the power-on default values will not provide output clock waveforms. And how I can programmed my SH interval? The number of pixels between SH Intervals (aka the line length) is set in Register Page 2, Address Dh, Eh and Fh. The waveform behavior during the SH interval is controlled by the settings of Register Pages 3, 4 and 5. To select my INCLK = PIXCLK I have to make this configuration (page 0, register 02, bit 2 = 1) but in the register settings that you sent me its written SPI_SENDDATA(0x02C2); To set INCLK = PIXCLK we need to set bit 2=1. For a 3 output CCD sensor I would recommend setting Page 0, Register 2 to C6h. This will give: 3 channel input mode Normal RGB data ordering MCLK at PIXCLK frequency CDS sampling Standard CCD Sensor Type (Does not have even/odd transfer array architecture) If we sent a file with this register set to C2h that was in error. My apologies. Please also tell me how to do a serial interfacing to send data to ADC chip. The serial interface must comply with the sequence/timing shown in Figures 62-67. There are a few different possible modes of operation of the interface that should provide the needed flexibility to allow a wide range of control devices (ie. uC, uP, FPGA) to work with the LM98725 . Regards, Hooman
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