Chen, We are using our own board design, not an EVM. An update on our progress, we got the LVDS partially working (there was a bug in the FPGA that made it send wrong SPI commands, now that is fixed), D3 and D4 now appear to be outputting something, and when I set the test pattern to all 1 or all 0, the D3 and D4 LVDS lines stay at high or low as expected. Now we have some more problems: - D2 and D1 LVDS outputs do not work, they appear to be stuck at 1 no matter what D3 and D4 are doing. - Reading the registers on our FPGA, it looks like the AFE is not sending the sync word (0x2772), but we are not sure if this is the FPGA not reading properly or the AFE not sending a sync word. If the LVDS is sending data, should it automatically send the sync word even under test pattern mode? We are sending the following ADC register commands over SPI. Addr 0x00: 0x0001 Addr 0x01: 0xC000 Addr 0x02: 0x6000 Addr 0x03: 0x2000 Addr 0x04: 0x0010 Addr 0x05: 0x3F80 (obviously this isn't used because addr 0x02 isn't set to custom, but we kept it anyways) Addr 0x0A: 0x0100 Addr 0x16: 0x0001
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