Hi Christian, Please refer to the thermal modeling of the LM98725 attached: (Please visit the site to view this file) The model shows the top of the case being pretty close in temperature to the junction. If you can monitor the top of the package in different conditions, and ensure that the top stays below 110C then it should be OK. The temperature you’ve measured on the LM98725 is in-line with what we’d have expected based on simulation results. Here are some highlights: In the models generated, the case top and die temperatures were within 1 degree C, as shown on page 4 of the file. So if you measure the temp at the top of the package with a fairly low thermal load probe you should get a reasonable picture of the die temperature. • Theta JA Improvement of 23.2% with 4 layers JEDEC Boards – Theta JA with 2 lyrs JEDEC Board: 83.31 (deg. C/W) – Theta JA with 4 lyrs JEDEC Board: 63.96 (deg. C/W) • Junction temp, Tj Improvement of 17.2% with 4 layers JEDEC Boards – Tj with 2 lyrs JEDEC Board: 84.90 (deg. C) – Tj with 4 lyrs JEDEC Board: 70.29 (deg. C) Based on the “typical” power dissipation of 0.755W in LVDS output mode at the max clock rate (81 MSPS ADC rate) we arrive at a junction temperature of 108 degrees for an ambient temp of 60 deg. C with a 4 layer board (Theta JA = 63.96 deg. C/W. Adding multitude of vias from device pin pads to inner layers of the board always help a lot if you can or have already incorporated on your board. Regards, Hooman
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