Hi Martin I'm trying to understand what is preventing the PLL Lock Detect bit from being set. I reviewed your schematic again and I wanted to confirm what logic level you are setting on the /RESET pin of the device. It is connected to M-3. Since this is active-low, this signal should be either floated to allow the built-in pull-up to hold it high, or driven to logic high from whatever it may be connected to. You shouldn't need to apply a RESET signal to the device but it is good to have it available in case it is needed for other debug purpose. To answer your earlier question, the register settings of the device are volatile. Every time the power is turned off the register values are cleared. Can you try applying a somewhat faster or slower INCLK signal to see if this has any effect on the PLL Lock bit? I did notice in your oscilloscope images that there is a lot of ringing on the rising edge of the INCLK signal. Is this due to a long ground lead on the oscilloscope probe, or does the signal at the INCLK input really have that much ringing? If the ringing is real that could cause problems. In that case it would be good to add some series termination at whatever is generating the INCLK signal. This will reduce the edge rate and the ringing. Please let me know the answers to these questions. I'll let you know if I think of any other issues that would prevent the PLL from locking. Best regards, Jim B
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