Forum Post: RE: TX_SDK_V1 ultrasound Tx Evaluation kit broken?
Hi Shuai Na, The power up sequence for the LM96551 on the TX-SDK-V1 is essential, or the chip will get damaged . I think the other devices on the EVM are not affected. If you can send me the EVM plus...
View ArticleForum Post: RE: Using LM98725
Hi Martin I've started reviewing your Registers data.txt file and noticed that the Writes you're intending to do to Page 0, Register 0 may actually be Reads. The SPI transfer value sent for those...
View ArticleForum Post: RE: Using LM98725
Hi Jim, Yes you have interpreted it correctly because I was reading the Register 0 at that time but I have tried it with 0x2023 and the result is same. I'm getting the same signal from both PHIA1 and...
View ArticleForum Post: RE: Using LM98725
Hi Martin Your configuration settings (other than Page 0, Register 0) look OK, but I'm not sure the configuration sequence you are using is completely correct. Please confirm you are now following the...
View ArticleForum Post: RE: Using LM98725
Hi Jim, Yes I'm configuring the registers as per instructions in the 7.5.1 section. As you can see my first register write command is 0x2022 which means page 0 register 0 bit 0 = 0 and then I configure...
View ArticleForum Post: TI-SDK-V1/XEM3001 USB driver
I am using the TX-SDK-V1 in Windows 10. The driver for the XEM3001 board is not installed automatically, and Windows says it can't find a driver for it. I contacted Opal Kelly to request the driver,...
View ArticleForum Post: RE: Using LM98725
Hi Martin Sorry, I didn't see a write of 22h to Page 0 Register 0. Can you send the updated register write sequence you are using? Per datasheet section 7.4.25, the input clock should be either stopped...
View ArticleForum Post: RE: Using LM98725
Hello Jim, I have attached an updated Registers configuration file, please have a look. Today I configured the registers with this sequence while +INCLK was applied continuously and I get some sort of...
View ArticleForum Post: RE: TI-SDK-V1/XEM3001 USB driver
Hello Paul, We have not tested the TX-SDK-V1 in a Windows 10 to see if it works or not. We've verified operation with Windows 7, according to what is on the web page: "The LM96530 T/R Switch, LM96551...
View ArticleForum Post: RE: AFE58xx Vin hi and low
Is anybody from TI on this forum? Can somebody from TI please answer the question above?
View ArticleForum Post: AFE5803 Interfacing
Hi, In AFE5803 datasheet (Page 48) LVDS trace difference length is given as <3.81mm. Am I correct in thinking that this contraint is that between LVDS pairs, or is it between traces in each pair, or...
View ArticleForum Post: RE: Using LM98725
When I read page 0 register 0 it shows that PLL is not locked, how can I solve this issue?
View ArticleForum Post: RE: Using LM98725
Hi Martin I'm trying to understand what is preventing the PLL Lock Detect bit from being set. I reviewed your schematic again and I wanted to confirm what logic level you are setting on the /RESET pin...
View ArticleForum Post: RE: Using LM98725
Hello Jim, I think the ringing on the rising edge is may be because I'm using passive probes with the oscilloscope. The /Reset pin status is floating, its just connect to a connector M but there is no...
View ArticleForum Post: some questions about LM98620
Hi, My customer is using LM98620 on ATM project, now there are some questions need you comment. When OVBP is active low, is LM98620 still workable? Can registers be configured by SPI? How to connect...
View ArticleForum Post: AFE5809 Schematic
Hello, For My application, I am not going to use AFE5809 in CW mode. I will be getting VCA input (J1-J9), ADC clock from (J15 also removing onboard clock for ADC) and TX_Sync_Pulse for my application....
View ArticleForum Post: RE: Using LM98725
Hi Jim, I have tried INCLK with different frequencies but same result PLL unlocked and output waveform is random.
View ArticleForum Post: RE: AFE5803 Interfacing
Hi team, Please could you get back to the customer on this. Kind Regards Thileepaan
View ArticleForum Post: RE: Using LM98725
Hello, Any solution for the PLL locking? I'm waiting for your response.
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