Hi Martin, We have used your register settings (file attached) and your clock frequency (5MHz) on the LM98725 and we don't see any problems with PLL lock! (Please visit the site to view this file) We'll next convert our setup to single ended clock (it is currently using LVDS differential clock) to see if we can recreate the PLL not lock that you are experiencing. I'll keep you posted as to what we find out. Regards, Hooman
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