Hi Hooman, Today I was working on the project and used 3MHz CMOS clock from FPGA, I notice an unusual condition for the PLL lock. When I start my FPGA and Lm98725 circuit for the first time the PLL don't get locked but if I restart my Lm98725 circuit only and not FPGA the PLL gets locked and generates output clock pulses. I don't know why is this happening, can you tell what could be the reason behind this saturation? I have attached both pictures of the clock pulses on the first start without PLL lock and after restart picture.
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