Today I used 3MHz CMOS clock, I notice an unusual condition for the PLL lock. When I start my FPGA and Lm98725 circuit for the first time the PLL don't get locked but if I restart my Lm98725 circuit only and not FPGA the PLL gets locked and generates output clock pulses. I don't know why is this happening, can you tell what could be the reason behind this saturation?
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