Hi Martin, One question: Is your PLL unlock issue resolved now? How did you resolve it? I got the following information from Jim who helped you earlier to help you adjust the PHIA : "It’s probably not obvious what he needs to do, but it’s pretty straightforward. His current settings for the PHIA timing are: Page 6 Address Data (all in hex) 20 00 21 00 22 00 23 1F 24 FF 25 FF This gives a string of 0s and 1s as follows: 000000000000000000000111111111111111111111 There are 21 0's followed by 21 1's. This digital pattern is clocked out of the PHIA high speed timing generator (bit period is 1/42 of the pixel period) over the duration of one pixel period, giving a 50% duty cycle period with the first half low and the second half high. The pattern can be rotated left or right to change the rising and falling edge points with respect to the pixel period. So if he wants to make the rising edge occur later he can change the pattern to this: 111111100000000000000000000011111111111111 The corresponding Page 6 register values are: Address Data 20 03 21 F8 22 00 23 00 24 3F 25 FF To make the rising edge earlier with respect to the pixel boundaries he can do this: 000000000000001111111111111111111110000000 The corresponding Page 6 register values are: Address Data 20 00 21 00 22 0F 23 FF 24 FF 25 80 So he can arbitrarily shift the relationship between the SP (Shift Pulse) and CP (Clock Pulse) as needed." Please let me know the PLL lock status and try the scheme Jim has outlined above and let me know. Regards, Hooman
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