Hello Hooman, Regarding PLL lock I have mention it in my earlier post that when I first turn ON the LM98725 circuit and configure it the PLL remains unlock. It gives a random signal on output but when I restart the circuit and turn it ON again the PLL gets lock. I don't know why its happening that PLL is not getting lock in first attempt. On Monday I'll try to configure PHIA1 clock as Jim as mentioned. One more thing, I want to use LM98725 in Slave mode using FPGA to give SH_R pulse. I have configured Page 0 Register 0 as 0x2020 (Bit 1=0) but the LM98725 is already outputting PHIA1 and SH1 clock signals without applying any external pulse for SH_R, how can I configure it in slave mode. I'm also not getting CMOS Data CLK on SH2 for my FPGA and how can I configure a signal for FPGA to know when each new line is starting? Thankyou
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