Circuit schematic is same without any changes but I' have attached an updated version of registers data. If I configure Page 0 Address 4 Bits [2:0] as 010 this means the reference voltage on the VCLP pin is now 95% of the input sensor voltage correct? so the LM98725 will consider the output that is above this value? In sample and hold mode my Clamp and Sample pulse should arrive at the same time? (Please visit the site to view this file)
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