Hi Alex, 1. This is a non spec parameter. My recommendation is min reset time at least 4 INCLK. That's no max time limitation. 2.This is a spec parameter: LVDS Output: Min=180mV, Max=450mV with Rl=100ohm 3. TXCLK Tr/Tf is affected by external conditions: Tline impedance and losses and receiver load. Based on estimation and bench measurements for a good matched system fastest Tr/Tf is a least 1nS. My recommendation is not to slow it down more than 1/3 of LVDS Data bit cell(TXCLK/7) 4.Datasheet has typ values for the toughest conditions at the highest freq. The internal delays will have a smaller impact at lower freq(16.65MHz), all these timings are percentage wise much close to the ideal transition: N*TXCLK_period /7 where N is the data bit order. Regards, Costin Costin
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