Kriby and Christian, Sorry for the delay; I meant to write you yesterday. I am fairly certain I have identified the problem. I found that my FPGA development board was sending additional, erroneous write commands to the AFE, above and beyond those I would expect based my software commands. Using an oscilloscope, I had previously confirmed that the timing requirements were being met and that the data was correct. However, until my further testing, I hadn't captured one of the erroneous write commands. I believe this fully explains the behavior I am seeing. I want to implement further testing of the HDL before re-programming the FPGA, so I cannot confirm full functionality just yet. I have one last question before you can close this thread. What is the expected result when writing to status bits and reserved bits? For example, if I were to write a 1 to the False Lock bit, should I expect to read a 1 from it on the following cycle? Or are writes to status bits ignored? What about reserved bits? Thanks for all of your help. Sorry for the issue on my end. I had suspected there was a problem with the HDL, but the oscilloscope was telling me otherwise. In the future, I'll be sure to consider that it might be missing something. Bradley
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