Kang, Again thank you for the quick reply. The app note you sent are very interesting and may be useful as we move farther in the design but they do not answer my question. We are doing all our measurements using the TI EVM. We are not using the PLL internal to the DAC3482 . I have verified that bit 10 of register 0x18 is set to 0 so the PLL should be bypassed. We are not using the clock distribution chip (CDC62005) we are inputting the clock directly to the DAC on J22. We have tried many different combinations of clock and output frequencies all of which still have the pedestal response in the phase noise below 200 kHz offset on the output signal. The level of the phase noise changes with the ratio of the output frequency to the clock frequency as you would expect but I don't understand how the output phase noise is higher then the input. The noise out should be lower then the noise in in proportion to the divide ratio as long as you are above the noise floor of the DAC. The picture below shows the input clock (1 GHz) and the output signal at 460.8 MHz from an Analog Devices DDS chip AD9912. The output phase noise should be 20 LOG Fs/Fc. 20 LOG 460.8/1000 = -6.73 dB. As you can see the output noise follows the shape of the input and is very close to the theoretical value. Am I wrong to expect a similar result using the NCO in the DAC3482 ?
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