Part Number: ADC12J4000EVM I have a question about the sample mapping for the ADC12J4000EVM . I have organized the samples from the JESD204B interface according to Table 12 and Table 13 in the datasheet. However, I am experiencing incorrect results when validating. I just wanted to confirm that I am not misinterpreting the datasheet. The start of frame for the interface in this design is reading out at '1000', which from the datasheet implies that the bit mapping follows the organization in the attached tables below. Would you be able to confirm that this is correct? I am using the TSW14J10 breakout board to interface with a Xilinx VC707. Thanks in advance, Steve M Sample Mapping [SOF = '1000'] Character Mapping:
↧