Todd, Section 7.3.2 and section 7.3.3 are strictly highlighting the SERDES PLL, which is different than the DAC PLL (7.4.12). The SERDES PLL will basically take a reference clock (a divided down clock from the DAC PLL or directly from external clock, user selectable from register SERDES_REFERENCE_CLK_SELECT) See below registers This reference clock can be divided down by serdes_refclk_div and also multiplied up through MPY value The final required SERDES PLL rate depends on your line rate. We typically use full rate. For instance, with 10Gbps of SERDES line rate, your SERDES PLL need to be 2.5GHz. -Kang
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