Forum Post: RE: ADS1256: INA188
Okay Chris. Thanks. Your explainations have helped me to understand better. A last question: " I think you will need the +/- 12.5A current to result in an input voltage that swings +/-1.5V around a...
View ArticleForum Post: RE: AFE4900: If there is no MCU to send out CLK to AFE4900, could...
Hi Lian, Since AFE4900 is shared under selective disclosure, lets take this discussion offline. I will send you the message. Regards, Prabin
View ArticleForum Post: RE: AFE4300: AFE4300
Hi David, Pleas refer to the following image in the above mentioned page for using 4 load cells. Here each load cell have 3 wires. Regards, Prabin
View ArticleForum Post: RE: ADS1261: ADS1261: need of sample rate different from default
Hi Marco, Please take a look at section 9.4.1.3 and Table 8 in the ADS1261 datasheet. There is some conversion latency in pulse mode that's coning to make it difficult for you to achieve an 8kSPS rate...
View ArticleForum Post: RE: DAC38J84: Which register is configtbd ?
Hello, The first configtbd is the alarm registers located from config100 (0x65) to config109 (0x6E) The second configtbd is located in config3 with respect to the DAC output gain the third configtbd is...
View ArticleForum Post: RE: DAC161S997: DAC Output Problem
Hello, Okay, understood about the 24V loop supply. Do you have a schematic of your hardware that you could provide? Have you tried reading back the DAC data register as well as the alarm register as I...
View ArticleForum Post: RE: DAC38J84: What are the semantics of CDR rw_cfgrx0[18:16]?
Todd, you may refer to attached information for CDR setting. By default, we have tested CDR setting of 000 for JESD204B. You can tweak your CDR setting and use along with PRBS testing highlighted in...
View ArticleForum Post: RE: DAC38J84: Documentation Question: Do Manual Sections 7.3.2...
Todd, Section 7.3.2 and section 7.3.3 are strictly highlighting the SERDES PLL, which is different than the DAC PLL (7.4.12). The SERDES PLL will basically take a reference clock (a divided down clock...
View ArticleForum Post: RE: Linux/ADS7828: device driver for ADS7838
Hello, You will need to connect the I2C - SCL & SDA pins (Pins 14 & 15) of the ADS7828 to the pins you configure to the the I2C port of the E3845.
View ArticleForum Post: RE: ADS52J90: ADS52J90 ADC clock source
Hi Prateek, How are you? According to the ADS52J90 data sheet of the power consumption estimation: When using LVDS mode: When using JESD mode: Please take a look. Thank you for using ADS52J90 device....
View ArticleForum Post: TINA/Spice/ADC12DL3200: TINA/Spice/ADC12DL3200
Part Number: ADC12DL3200 Tool/software: TINA-TI or Spice Models Dear Sirs, I'm designing a board that uses two ADC12DL3200 connected at one FPGA Xilinx. The FPGA downloads the data and drives the...
View ArticleForum Post: RE: ADC10D1500RB: ADC10D1500RB/NOPB
Hi user I've discussed this with our sales team in your region who should be in contact with you. They should be able to help you purchase these boards through a different method. Best regards, Jim B
View ArticleForum Post: RE: TLV5626: Does TI have noise model for TLV5626？
Hi Fawn, Thank you for your query. Unfortunately we don't have a noise model for this part. Regards, Uttam Sahu Applications Engineer, Precision DACs
View ArticleForum Post: RE: ADS124S08: ADS124S08 VS AD7124-8
Hi Alex, you will receive an email later today from me. Regards,
View ArticleForum Post: RE: TINA/Spice/ADC12DL3200: TINA/Spice/ADC12DL3200
Hi Daniele If you want to align or synchronize the data between the two ADC12DL3200 devices the SYSREF inputs must be driven in a way that is frequency locked and phase consistent with the 3200 MHz...
View ArticleForum Post: ADS1274: SPI working
Part Number: ADS1274 Hi, I'm working with a ADS1274EVM board in mode FS and a DSK6455 processor. Now I'm developing a board based on the 6745 processor, but I need that the ADS1274 /8 works in SPI...
View ArticleForum Post: RE: ADS5444-SP: timing analysis questions
From measurements, I confirmed that as the clocking period increases the setup and hold times increase equally. Thanks Christian
View ArticleForum Post: RE: TINA/Spice/ADC12DL3200: TINA/Spice/ADC12DL3200
Hi Jim, thanks for your suggestions. In my case, I don't use the LMK04828 . For this reason, I've asked if i could drive the SYSREF with the LVDS driver. Could you help me? Thanks in advance.
View ArticleForum Post: RE: TINA/Spice/ADC12DL3200: TINA/Spice/ADC12DL3200
Hi Daniele If you need to drive the SYSREF inputs from an LVDS driver you should AC-couple the connection. The SYSREF input common mode voltage must be between 0V and 0.55V. This is not possible using...
View ArticleForum Post: RE: ADS1278-SP: Performance fSCLK/fCLK
Hi, The device is spec'd to allow a master clock of 100kHz to 32.768MHz so a 13.0MHz clock is fine. Thanks Christian
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