Hi Moti, - Using DACCLKSE will not change the connections to FPGA. DACCLKSE and DACCLKDIFF are connected to a 2:1 mux that selects one of these 2 inputs. See figure 52 in the datasheet. - You dont need all 3 inputs, you only need one clock input and SYSREF -You only need to make sure that there is a fixed timing relationship between SYSREF and the DACCLK always. If you will be using the 6GHz external clock as the DACCLK, then I will suggest you look at the SYSREF capture circuit in datasheet section 8.3.10. This will help you to reliably capture sysref for synchronization. Thanks, Eben.
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