Part Number: ADS5263 Hi, I would like to interface a quad channels ADS5263 in LVDS/2wires/8xSerialization mode to a FPGA. I was wondering if it would be possible to use the frame clock (ADCLK) to drive a PLL to generate the bit clock inside the FPGA (bit clock LCLK from ADC is therefore not used). Timing closure at high speed (ADC at 80Msps) is tricky to achieve. Since the frame clock seems to be generated the same way as data the idea is to save timing margin compared to the using of bit clock LCLK to latch data. Unfortunatly there is no timing infomation in the datasheet concerning the data position relative to frame clock... What is your opinion about this method? Best regards, Gauthier
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