Part Number: AFE5401-Q1 Hello, I have a question regarding the option DSYNC1_START_LOW in register 24. When I select this function, what implications does it have on the timing depicted in Figure 67 of the AFE5401-Q1 datasheet? In detail: Are the low and high phases of DSYNC1 within COMP_DSYNC1 swapped? What happens with the DSYNC1_HIGH time? Kind regards, Tobias
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