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Forum Post: RE: ADC12DJ3200: The SYNC signal between ADC and Xilinx FPGA not stable

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Hi junsha Are you using the JESD204 IP Core from the FPGA vendor? Is this design based on the Xilinx or Altera example firmware found here? Look under the Software heading part way down the page. Generally some error in the received data will cause SYNC to be asserted. What errors are being reported by the RX IP prior to SYNC being asserted? Best regards, Jim B

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