Hi Chen, Thank you for this answer. We use an Intel CycloneV GX (5CGXFC9E6F35C7) FPGA which doesn't seem to have DPA (Digitla Phase Alignment circuitry). I have already implemented capture scheme using delays (Figure 4-2 in sbaa205.pdf) and timings are met with a sampling clock up to 40Mhz (data rate of 320Mbps). At higher frequency timings are not met at all corner cases. I wanted to try ALTLVDS_RX but with the frame clock as input clock. Since the frame clock is aligned with data, doing this way supress the need of frame alignment (bit slip). Thanks, Gauthier
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