Watanabe-san: I have a couple of questions/observations. You are injecting a 3-GHz clock to the DAC as the sampling clock and not using the internal PLL/VCO. Indeed, the phase noise should track the RF sampling clock . What did you mean by: "We are evaluating other DACs by similar way but DAC38RF82 data is the worst so far". Are you saying that other devices do track but that the 'RF82 does not? The E8257 performance looks good. You see the expected 20 dB delta from 100 MHz to 1 GHz. Initially the noise floor jumped out to me. The measurements are in dBc/Hz so the performance is relative to clock/signal strength. The E8257 at 100 MHz is showing a floor of -180 dBc/Hz which implies a high output power. The DAC measurements are likely at a much lower level, If you convert each to a dBm number I expect the performance of DAC to E8257 to be close with the advantage to the test equipment as there are no other noise sources in that case. Another concern is the clock signal swing getting to the device. The EVM's external clock input circuit was not originally designed for such a low frequency. There is likely a lot of insertion loss within that pass. As a quick compensation, you can juice up the clock signal very high (~18 dBm) to overcome the insertion loss of the input network. Alternatively, you can tweak the network by removing unnecessary chokes and optimizing the balun for best signal transfer at 3 GHz. --RJH
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