Chris, Thanks for the response. Thanks for the links, those were the ones i was looking for - i need to implement pretty much exactly the same scenario that Mahesh described for his user. I have few more questions - a) you mentioned with 16kSPS data will be ready in 408uS - can the device we configured for 16kSPS and assuming a 4.096MHz clock, shouldn't the data be ready in 63uS? What am i missing? b) When i attempted to do switch channels - Write Config 1 register, and then issue RDATA - the chip seems to be going dead - i.e no more DRDY going low. Not sure what i am doing wrong. However if i issue the config 1 register update when i boot up, the register update seems to hold. If i put the chip in RDATAC mode, can i switch channels between DRDY at all? That thread was great teaser, stops right where one thinks here is the anwser :). Additional question is - should i add another ADS1282 to handle the second channel instead of muxing. Thanks santosh
↧