Hi Brian, The short pattern transport layer testing is purely testing the transport layer (i.e. data packing layer) between the FPGA and DAC. This should be done after the phyiscal layer testing (i.e. PRBS test) over the SERDES link itself, and the link layer testing (i.e. K28.5 handshaking code test). I am assume the current JESD204B link is fine (i.e. link established) and therefore the customer is testing the short pattern test. If the link is not OK, then the user need to double check the link before performing the transport layer test There is an app note to show users the test modes for the DAC38RF8x family: www.ti.com/.../slaa750.pdf -Kang
↧