Brian, Based on my understanding of the other similar devices, the JESD handshaking protocol is before the lane mapping cross bar. This means that the Lane ID check is checking the physical lanes. You will have to wait for Eben to confirm on this The SERDES inversion need to be checked thoroughly from FPGA pin out, FPGA transceiver configuration, PCB routing, and all the way to the DAC SRX lanes. The INVPAIR bit in the register map of the DAC will need to be checked For the JESD_SYNC_REQ register, you should at least at a minimum set to 0x03 per JESD204B standard. This will check the CGS and the 8b/10b errors to start the hand-shaking. If the lane ID (or part of the link configuration check ILAS) is giving you problem, you can set this register as 0x00DF to "ignore" the ILAS check. Please note this is different than "skipping" ILAS. Skipping ILAS is a sublcass 0 approach, which is not support officially in subclass 1. Ignoring ILAS simply checks the error, but ignores it. The FPGA is still expected to send out ILAS on the 2nd multi-frame after the K28.5 char stops The TSW14J56 is currently using Altera's JESD core, not the MEGACORE IP, I believe. We migrated to Altera a long time ago. My understanding is that the Altera IP always have a hard time sending out proper ILAS pattern (i.e. including Lane ID). This is the reason that we just set JESD_SYNC_REQ to 0xDF to ignore ILAS completely. I will ask Eben to check on the Lane ID when he gets back. below ppt shows the DAC38j84 sync request structure. -Kang(Please visit the site to view this file)
↧