Forum Post: ADC128S102QML-SP: Can I stretch the acquisition time to increase the sampling accuracy

Part Number: ADC128S102QML-SP Hello, The datasheet mentions that the SCLK frequency must be within 0.8MHz to 16MHz. In order to allow for a long acquisition time but a short conversion time, could I drive the first 3 cycles of SCLK slowly (say 1us period) and drive the remaining 15 cycles faster (say 100ns period) ? Thank you for your help