Hi Dean, Welcome to the TI E2E Forums! To answer your questions.. The decimation ratios are absolute; however as you pointed out, the data rates will scale with the f CLK frequency. There is pipe-lining only in the sense that as soon as a conversion completes, the ADC will begin a new conversion right away, meanwhile the calibrated conversion result is computed and /DRDY goes low while the ADC is performing the next conversion. However, since this is a multiplexed ADC, there is only a single delta-sigma modulator and digital filter; therefore, it is not possible to perform any kind of simultaneous or concurrent sampling of both input channels. When re-configuring the ADC (changing the MUX, for example), the digital filter and all its taps are reset. The previous conversion is halted and a new conversion begins. Therefore, the settling time will be the full 63-conversion periods for the filter taps to acquire enough data to compute a "settled" result. NOTE: If you use the SINC5 filter, then the digital filter settling time will be approx. 5 conversion periods instead of 63 conversion periods with the FIR flat-pass band filter. There is not a 24-bit data mode per se... There is a modulator bitstream mode, or 31-bit filter data mode (the 32nd bit is a redundant sign bit). You can, however, clock out the first 24-bits of data and stop the SPI communication after that if you are only interested in 24-bit data. Best regards, Chris
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