Part Number: DAC38RF89 Currently experiencing what appears to be a delay offset between I and Q data (potentially a delay difference on a lane basis i.e. individual bytes). I can't tell from the datasheet what the data path looks like. The datasheet refers to a JESD_FIFO and a JESD_RBD_Buffer (don't know if these are one in the same or independent). My assumption is that the JESD write is not an issue (protocol will align data). However like to understand what mechanism are available to synchronize the reads.
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