Hi Ken, 1. This cap should be directly on MOD_OUT. It is possible that the output modulator will be unstable and oscillate without it. Probably will be okay in most cases but in the final design you should add this cap. 2. Understood, I see that now. I would be interested in seeing the output waveform you described earlier. In the first section line 631 seems to succesfully write something to the FIFO as the empty flag is low after that particular write. You can't verify the contents of the FIFO by reading FIFO_D2M as the data bits are write only. After writing CTS you can read FIFO_M2D if the device is in full-duplex mode to see the transmitted data. But, you should also see the modulation on MOD_OUT. Thanks, Garrett
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