Hi Oba, I understand the figure you are showing, and you are correct about which edge would be considered the first edge that data would be latched. We have based our specification on the first falling edge of SCLK after the falling edge of SYNC being the first clock edge that the DIN is valid (DB23). If condition 2 or condition 3 occur, then our timing specification is being violated and the frame is invalid (in that DB23 is not being latched in the correct position). Is your concern that condition 2 or 3 may occur in your system? If that is the case then I think the architecture of the SPI master must be re-evaluated to ensure the signal is more coherent. Thanks, Paul
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