Hi Gil The TMSTP+/- inputs use similar input circuitry to that of the CLK+/- and SYSREF+/- inputs. This was done to give better performance matching between those inputs and the signal applied to TMSTP. Unfortunately this means the DC-coupled TMSTP or /SYNC signal must meet the low common mode voltage requirements, which is not compatible with LVDS. There is no way to convert from the FPGA LVDS outputs to the TMSTP+/- inputs using discrete terminations. Using a resistor divider to achieve the needed common mode will result in the differential amplitude being lower than what is needed. The only solution is to use an LVDS to LCPECL or LVPECL buffer IC along with some additional board level termination resistors and set TMSTP_LVPECL_EN = 1. When using an FPGA LVDS output for JESD204B /SYNC a conversion IC is needed in either case. Therefore for simplicity we recommend using the /SYNC_SE input instead of the TMSTP+/- inputs. Best regards, Jim B
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