Hi FloW, The 47 Ohm resistors on the digital lines slow the clock edges to help reduce noise. This has no effect on DRDY. I'm not sure I'm following the SDI and the 1Meg resistor. That shouldn't make any difference. The way you should have your interrupt setup is to take the DRDY signal (which is an always driven output of the ADS1248 ) and connect DRDY to a GPIO input that triggers on a falling edge of DRDY. Take a look at Figure 70 on page 36 of the datasheet. If you don't read any data from the ADS1248 , you will see a pulse that occurs on DRDY that follows the data rate configured for the ADS1248 . DRDY will go high for a slight period of time which is the update period. When DRDY goes from high to low, new conversion data are available. If you read the results, note how DRDY goes high after the first SCLK. So if you read the results, then DRDY will stay high most of the time. Your interrupt should fire on the edge transition from high to low state from DRDY. As soon as you clock out data, DRDY will go back high. The end of the conversion and new results are ready are signaled on the high to low transition of DRDY. Best regards, Bob B
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