For better support, we are in the middle of engaging the best person to support this device. In the mean time, please confirm the followings: When the link fails, what is the state of SYNC signal? Please, describe the procedure of the test condition more precisely. 1) at what temperature the initial link was established? 2) When failing at low temp, was the resync tried? Is it successful? 3) If initial link was established at low temp, do you see the proper data? 4) From FPGA side, what errors are reported? Does JESD_RX on FPGA have equalization feature? What happen if the equalizer is retrained at low temp? Regards, Hunsoo
↧