Hi Lakshmanan, For AFE5809 device's LVDS output circuitry, please take a look at the data sheet Figure 81. Equivalent Circuits of LVDS Outputs (on page 47). Its LVDS data directly DC outputs sent to your FPGA (for example). However, please also take a look on page 17: LVDS OUTPUTS spec: The Output differential voltage = 400mV and the Output offset voltage (Common mode voltage) = 1100mV. These conditions needed to fit (for example) your FPGA device. The SDOUT output pin follows the data sheet 1) from page 10, Pin Functions table shows The designer can use 1.8-V logic. 2) if needed to change level, from page 49, 8.5.1.2 ADC/VCA Serial Register Readout Description describes: Level shifter SN74AUP1T04 can be used to convert 1.8-V logic to 2.5-V/3.3-V logics if needed. Thank you! Best regards, Chen
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