Forum Post: RE: DAC37J82: DAC37J82 NCO and Mixer Configuration
Hi Thang We have received your question. One of our DAC experts will respond soon. Best regards, Jim B
View ArticleForum Post: RE: ADS5296A: Full scale ramp test pattern output format
Hi Niall, Thanks for letting me know. Yes, you are settings are correct. Also the full scale ramp pattern should show you: 1) when you setup to 10bit mode register, the captured ramp pattern supposed...
View ArticleForum Post: RE: AFE5809: Whether AC coupling required for LVDS Bit clock,...
Hi Lakshmanan, For AFE5809 device's LVDS output circuitry, please take a look at the data sheet Figure 81. Equivalent Circuits of LVDS Outputs (on page 47). Its LVDS data directly DC outputs sent to...
View ArticleForum Post: RE: ADS1115: Question about voltage divider
Once again thanks for your reply! Wow indeed I totally overlooked that!, you are right on that and yes, now, I think I am comfident enough to order the parts and get to it. Thanks for your patience and...
View ArticleForum Post: RE: ADS131E04: Propagation Delay between CLK to DRDY?
Martin, I'm still not entirely sure what you are asking for. I assume that you are referring to SCLK (from the SPI communication) instead of CLK (which is the master clock typically run at 16.384 MHz)....
View ArticleForum Post: RE: ADS1115: Question about voltage divider
Bryan, No problem. I still have concerns that the mechanical structure of the switch will limit the resolution of the measurement. However, you should be able to construct this without too much problem...
View ArticleForum Post: RE: LM98640QML-SP: LVDS timing
Timing specs are typically provided at the fastest clock frequencies as these specs become relaxed when the frequency slows. No other specifications are provided. Yes, the LVDS output clock is 50% or...
View ArticleForum Post: RE: LM98640QML-SP: SDO output voltage
Hi Bradley, Your observations are correct. We are aware of the contradiction and had expected this to be updated in the datasheet. We will determine why this has not been updated and try to correct....
View ArticleForum Post: RE: ADS1278-HT: ADS1278-HT and ADS1278-EP
TI does not release such information without an NDA and an understanding of the motivation for needing such information. Would you like me to contact you directly off the public forum to discuss this...
View ArticleForum Post: DAC902: EOL plan
Part Number: DAC902 Hello, Is there any plan to obsolete DAC902 seiries ? DAC902E DAC902E/2K5 DAC902U DAC902U/1K Regards, Miwa
View ArticleForum Post: RE: ADC12DJ3200: strange behavior vs temperature
Hi Vincenzo I've discussed this more with a few experts and we have a few theories and some debugging steps to try. 1) It's possible the RBD (receive buffer delay) setting in one of the JESD204B...
View ArticleForum Post: RE: ADS1278-HT: ADS1278-HT and ADS1278-EP
Christian-san, Thank you for your reply. I sent private message, so please check it. Best Regards, Kuramochi
View ArticleForum Post: RE: DAC902: EOL plan
Hello Miwa The DAC902 product status is shown as Active with all variants you have listed available for order and in-stock. You can click the Alert Me button to sign up for notifications if there are...
View ArticleForum Post: RE: ADS7946: ADS7946 REF short to REFGND
Cynthia, is there any requirement of power on and power down sequence for this chip? AVDD,DVDD,REF
View ArticleForum Post: RE: LM98714: CLKOUT(CMOS mode)
Costin-san, How is this situation? Best Regards, Kuramochi
View ArticleForum Post: RE: AFE4405: AFE4405 "I2C_SPI_SEL" and "CONTROL1" pin current flow
Hi, Since AFE4405 is still under NDA, let's take this discussion offline. Regards, Prabin.
View ArticleForum Post: RE: CCS: AFE4900
Hi, Since AFE4900 is shared under selective disclosure, let's take this discussion offline. Regards, Prabin
View ArticleForum Post: RE: CCS: AFE4900 initial
Hello, Can you please elaborate on what is not working? We used "Recommended register settings" (Table 144 and Figure 182) from the datasheet of AFE4900 . If the code does't work, I would recommend to...
View ArticleForum Post: RE: Compiler/ADS1298ECGFE-PDK: FFT results not matching with...
Yes i agree with you, i have set it to 16kSPS and 500 samples/CH after startup, it shows 500SPS and 1000 samples/CH during startup i.e by default. I have attached required screenshots. in this example...
View ArticleForum Post: RE: ADS5296A: Full scale ramp test pattern output format
Hi Niall, How are you? Please confirm with us that you are using ADS5296A EVM and TSW1400EVM on your test bench to run Full scale ramp test pattern. The data test results are captured from using...
View Article