Martin, I'm still not entirely sure what you are asking for. I assume that you are referring to SCLK (from the SPI communication) instead of CLK (which is the master clock typically run at 16.384 MHz). In 7.7 there is a propagation delay time given as tp(SCDOD). This time indicates the time from the rising EDGE of SCLK to setup the output data on DOUT. A change in SCLK directly changes DOUT. However, SCLK doesn't directly drive /DRDY. You can set up a conversion through a command, but the time that it takes to complete a conversion is based on the data rate. For that you wouldn't have a propagation delay spec. Even if you are referring to the master clock, the DRDY comes after a great number of master clock periods after a conversion is started. Generally there isn't a propagation delay specification from either clock to the /DRDY indication. Perhaps you could ask the customer to clarify the need for the specification. Joseph Wu
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