Eddie, Sorry I didn't get back to you earlier. It took me a bit to get something together. I was able to get an ADS131A04EVM to look at the device response (it should be the same as the ADS131A02 ). I used a logic analyzer to look at the startup waveforms and they basically look the way I expect. Here's a plot: When the device powers up, the starts the /DRDY, but the master starts with /CS low. In this case, it looks like the pulse train that I expect. After power up there are a few /DRDY pulses and then the master finally responds, but I think all it is providing at this point is null commands. The master then skips responses for a couple of /DRDY pulses and the device returns to the remaining pulse train. To me that was the part I wasn't sure about, but it's not completely unexpected. Without any /CS transition, there's nothing to return /DRDY high except for the completion of a conversion. After that, the device responds with a null command for each /DRDY and then you see the /DRDY mostly high. For your device, It seems like a similar response. The only thing that I found to be different is that your data period is a little different. In one of the scope shots where you first write and read from the ADC registers, it looks like you're missing a few /DRDY pulses (that is if you haven't changed the data rate). Note, I'm not sure if my logic analyzer is able to give the time resolution to decode everything sent to the device. I tried pulling out the SPI, but it looks like I'm sending way too few bits for each transaction. Let me know if this helped you in any way. Joseph Wu
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